In integrated circuit (IC) memory products, such as dynamic random access memories (DRAMs) and video random access memories (VRAMs), the amount of available memory on a monolithic chip is often referred to as the density. Density describes the total amount of memory fabricated on the circuit of the chip, such as 1 meg, 4 meg, and so forth.
FIG. 1 depicts a common DRAM array 5 containing a large number of memory storage cells 10. Each memory storage cell 10 is addressable by a unique row 15 and a unique column 20 address. If there are n rows 15 and m columns 20 the density is equal to nxm. In the example the density is equal to 8.times.2 or 16.
A memory device, such as DRAM array 5, accepts electrical data for storage through an input often called the "D" input. Electrical data read from the memory would be presented on an output called the "Q" output. In order to keep the package small the input and output functions are commonly combined to share the same pin which is now called a "DQ" pin 25. In the example, the complementary electrical data is available on the D/Q* pin 30.
FIG. 2 is a simplified block schematic of memory array 5 of FIG. 1. In FIG. 2 the block schematic indicates the actual manner in which the rows and columns are configured, 8.times.2. However when referring to a chip it is typically described by its total density, in this case 16.
Memory vendors often provide more than one configuration of a certain density product to better suit the needs of the consumer. In some popular variations the memory is split into 4, 8, 16 or more equal segments. These segments are accessed in parallel. Each segment of the array can be thought of as a subarray having a given density. Often m and n are equal in each subarray. The number of subarrays is referred to as the width of the memory array. In a memory containing subarrays, less row and column addresses are required for a total given memory capability since the density of each subarray is only a portion of the total memory density, and since the subarrays typically respond to the same row and column address. Such a configuration multiplies the "D" and "Q" pins required for transferring electrical data into and out of the IC. Each "DQ" pin services one of the afore mentioned subarrays which is then often referred to as a "DQ plane."
The division of the memory array into equal sided and commonly addressed DQ planes is very useful in certain systems which use IC memory. The various available configurations are often referred to as "by one", "by four", "by eight" and so forth. For example a 1 meg VRAM may be split into 4 DQ planes and is then referred to as a 256K.times.4.
Computers handle data in chunks of 8 bits at a time, so a by 8 product is appealing as a configuration for some monolithic memory chips. A by 16 product is also appealing for monolithic chips having high bandwidth applications. Since computers work on 8 bits at a time, at the by 16 level a method of writing to only 8 bits at a time is needed. This problem is solved by putting either two write control pins or two CAS pins on these chips.
For example, pages 2-115 through 2-131 of the 1992 DRAM Electrical data book by Micron Technology, Inc. describe the circuit configuration, timing, and functions of a MT4C1664/5L and are herein incorporated by reference to provide the reader with further information. The MT4C1664/5L is a 64K.times.16 monolithic DRAM memory chip featuring two write control input pins. One write control input pin accepts a WEL* signal and the remaining write control input pin accepts a WEH* signal, thereby allowing for a byte write access cycle. WEH* is the write enable signal to the upper byte which is represented by data at DQ9 through DQ16. WEL* is the write enable signal to the lower byte which is represented by data at DQ1 through DQ8. In this case WEL* and WEH* function in an identical manner to the typical normally low write enable (WE*) signal of a DRAM featuring a single write control input pin. Either WEL* or WEH* will generate an internal WE* through an AND gate. Thus if either WEL* or WEH* is active the entire chip goes into a write mode. However, only the bank having the active signal actually writes. The device can write to a byte or block the write to the byte. The block of the write to the byte is also known as masking of the write function. There is no Byte read cycle.
FIG. 3 is an example of a 2 Meg 256K.times.8 monolithic VRAM chip 34. A VRAM is a dual port DRAM used to store electrical data which can represent video images on a video monitor. When the electrical data represents video images it is referred to as video data. The serial access memory (SAM) port 35 accepts output video data from a SAM array portion 36 of the VRAM in a read mode and accepts external input video data in a write mode. Video data for controlling video images transfers quickly between the SAM 36 and SDQs 1-8 at the SAM port 35 either as video input or video output data. Random access memory (RAM) port 37 accepts internal digital electrical data from a DRAM array portion 38 of the VRAM in a read mode and accepts external digital electrical data in a write mode.
The DRAM portion 38 of the 2 Meg memory has been split into 8 DQ planes or subarrays. Each plane has a density of 256K. In a normal write, data is simultaneously written to a memory cell in each DQ plane. One address determines which cell is written, and each selected cell has the same address location in each DQ plane. Since eight cells are written, a byte of information is stored in the array during the normal write operation. During a block write, a block of cells are written in each DQ plane. Address input port 39 receives signals for addressing the selected memory storage cell within each DQ plane.
Row address strobe (RAS), column address strobe (CAS), transfer or output enable (TR/OE), input special function (DSF), serial clock (SC), and write enable(WE) are external input signals on external input pins 40,45, 50, 55, 60, and 65, respectively. These external input signals control internal timing and operation of a logic control generator 66. The logic control generator 66 generates an internal write signal, W.sub.1. These input signals are well known to those skilled in the art. Descriptions of the circuit configuration, timing, and functions of the 2 Meg MT42C8256 are found on pages 5-111 through 5-152 of the 1992 DRAM Electrical data BOOK by Micron Technology, Inc. and are herein incorporated by reference. The MT42C8256 is similar to the 2 Meg shown in FIG. 3.
In order to better understand the function of W.sub.1 it is necessary to have a better understanding of the configuration shown in FIG. 3. The SAM has been split into 8 subarrays in order that data may be transferred between a SAM subarray and a corresponding DQ subarray. Transfer gates 77, when activated, transfer electrical data between the DRAM portion 38 of the chip 34 and the SAM portion 36. A write transfer occurs when the data is transferred from the SAM to the DRAM, and read transfer occurs when the data is transferred from the DRAM to the SAM. The control signal W.sub.1 controls the operation of the transfer gates 77.
In the normal and block write modes electrical digital data is read from or written to the DRAM portion 38. W.sub.1 controls the normal and block write operation through the normal and block write control unit 80.
Due to the fact that ASCII codes need 8 bits of information, no less than 8 subarrays have typically been written at any one time. In this type of accessing a byte of electrical data can be written. However, when processing graphic data, a VRAM may have to work with a chunk of data at one time having 4, 8, 12, 16, 24, or 32 bits. This is due to the fact that the VRAM may be processing either gray scale or color data. There exists a need to provide a VRAM wherein a nibble of electrical data can be written to the monolithic memory chip. A need also exists to control the write to individual banks in the memory array independently of one another in order that one bank may be written during the same memory cycle that another bank is read.